公开(公告)号：US20150035563A1

公开(公告)日：2015-02-05

申请号：US14025058

申请日：2013-09-12

Applicant: Broadcom Corporation

Inventor： Ali Nazemi ,  Kangmin Hu ,  Jun Cao ,  Afshin Doctor Momtaz

IPC: H03K19/0185

CPC classification number: H03K19/018507

Abstract: A high speed level shifter interfaces a high speed DAC to the digital information that the DAC processes. The level shifter may convert CMOS level digital representations to, for example, CML level digital representations for processing by the DAC. The level shifter conserves the voltage swing in the CMOS level representations (e.g., about 1V). The level shifter also avoids voltage overstress, using a feedback loop to constrain the voltage amplitude, and thereby facilitates the use of fast thin film transistors in its architecture.

Abstract translation: 高速电平转换器将高速DAC连接到DAC处理的数字信息。 电平移位器可以将CMOS电平数字表示转换为例如CML级数字表示以供DAC进行处理。 电平移位器保存CMOS电平表示中的电压摆幅（例如，约1V）。 电平转换器还避免了电压过应力，使用反馈环来约束电压幅度，从而有助于在其架构中使用快速薄膜晶体管。

公开(公告)号：US09197214B2

公开(公告)日：2015-11-24

申请号：US14025058

申请日：2013-09-12

Applicant: Broadcom Corporation

Inventor： Ali Nazemi ,  Kangmin Hu ,  Jun Cao ,  Afshin Doctor Momtaz

IPC: H03K19/0175 ,  H03K19/0185

CPC classification number: H03K19/018507

Abstract: A high speed level shifter interfaces a high speed DAC to the digital information that the DAC processes. The level shifter may convert CMOS level digital representations to, for example, CML level digital representations for processing by the DAC. The level shifter conserves the voltage swing in the CMOS level representations (e.g., about 1V). The level shifter also avoids voltage overstress, using a feedback loop to constrain the voltage amplitude, and thereby facilitates the use of fast thin film transistors in its architecture.

Abstract translation: 高速电平转换器将高速DAC连接到DAC处理的数字信息。 电平移位器可以将CMOS电平数字表示转换为例如CML级数字表示以供DAC进行处理。 电平移位器保存CMOS电平表示中的电压摆幅（例如，约1V）。 电平转换器还避免了电压过应力，使用反馈环来约束电压幅度，从而有助于在其架构中使用快速薄膜晶体管。

公开(公告)号：US09344268B1

公开(公告)日：2016-05-17

申请号：US14668165

申请日：2015-03-25

Applicant: Broadcom Corporation

Inventor： Ali Nazemi ,  Burak Catli ,  Wayne Wah-Yuen Wong ,  Kangmin Hu ,  Hyo Gyuem Rhew ,  Delong Cui ,  Jun Cao ,  Bo Zhang ,  Afshin Doctor Momtaz

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04J3/0685 ,  H04J3/047 ,  H04L7/0025

Abstract: A phase alignment architecture enhances the performance of communication systems. The architecture aligns a divided clock (e.g., in differential Inphase (I) and Quadrature (Q)) to a main clock, even at extremely high speeds, where skew variations of the divided clock are comparable to the main clock period. The improvement in phase alignment facilitates ultra high-speed communications.

Abstract translation: 相位对准架构增强了通信系统的性能。 即使在非常高的速度下，分频时钟的分频时钟（例如，差分同相（I）和正交（Q））与主时钟对准，其中分频时钟的偏移变化与主时钟周期相当。 相位对准的改进有助于超高速通信。