公开(公告)号：US12007901B2

公开(公告)日：2024-06-11

申请号：US18171617

申请日：2023-02-20

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Tom Greenshtein

IPC: G06F12/08 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0891

CPC classification number: G06F12/0891 ,  G06F12/0238 ,  G06F12/0646 ,  G06F12/0846 ,  G06F12/0862

Abstract: An apparatus includes a cache memory circuit configured to store a cache lines, and a cache controller circuit. The cache controller circuit is configured to receive a read request to an address associated with a portion of a cache line. In response to an indication that the portion of the cache line currently has at least a first sub-portion that is invalid and at least a second sub-portion that is modified relative to a version in a memory, the cache controller circuit is further configured to fetch values corresponding to the address from the memory, to generate an updated version of the portion of the cache line by using the fetched values to update the first sub-portion, but not the second sub-portion, of the portion of the cache line, and to generate a response to the read request that includes the updated version of the portion of the cache line.

公开(公告)号：US20230259459A1

公开(公告)日：2023-08-17

申请号：US18171617

申请日：2023-02-20

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Tom Greenshtein

IPC: G06F12/0891 ,  G06F12/0846 ,  G06F12/06 ,  G06F12/02 ,  G06F12/0862

CPC classification number: G06F12/0891 ,  G06F12/0846 ,  G06F12/0646 ,  G06F12/0238 ,  G06F12/0862

Abstract: An apparatus includes a cache memory circuit configured to store a cache lines, and a cache controller circuit. The cache controller circuit is configured to receive a read request to an address associated with a portion of a cache line. In response to an indication that the portion of the cache line currently has at least a first sub-portion that is invalid and at least a second sub-portion that is modified relative to a version in a memory, the cache controller circuit is further configured to fetch values corresponding to the address from the memory, to generate an updated version of the portion of the cache line by using the fetched values to update the first sub-portion, but not the second sub-portion, of the portion of the cache line, and to generate a response to the read request that includes the updated version of the portion of the cache line.

公开(公告)号：US20250103520A1

公开(公告)日：2025-03-27

申请号：US18819755

申请日：2024-08-29

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Jurgen M. Schulz ,  Tom Greenshtein ,  Elli Bagelman ,  Brian P. Lilly ,  John H. Kelm ,  Rohit K. Gupta ,  Sandeep Gupta ,  Anwar Q. Rohillah

IPC: G06F13/16 ,  G06F12/0831

Abstract: A memory controller circuit receives memory access requests from a network of a computer system. Entries are reserved for these requests in a retry queue circuit. An arbitration circuit of the memory controller circuit issues those requests to a tag pipeline circuit that determines whether the received memory access requests hit in a memory cache. As a memory access request passes through the tag pipeline circuit, it may require another pass through this pipeline—for example, if resources such as certain storage circuits needed to complete the memory access request are unavailable (for example a snoop queue circuit). The reservation that has been made in the retry queue circuit thus keeps the request from having to be returned to the network for resubmission to the memory controller circuit if initial processing of the memory access request cannot be completed.

公开(公告)号：US20250103496A1

公开(公告)日：2025-03-27

申请号：US18433118

申请日：2024-02-05

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Amanvir Singh Sidana ,  Sandeep Gupta ,  Tom Greenshtein ,  Vivek Venkatraman

IPC: G06F12/0817 ,  G06F12/0891

Abstract: An apparatus includes a plurality of coherent agents, and a coherence directory that includes directory ways for storing coherency information. The coherence directory may be configured to determine that a cache block that is not currently cached among the coherent agents, is stored in a first coherent agent. The coherence directory may be further configured to, in response to this determination, create a particular entry in a selected one of the directory ways. The coherence directory may also be configured to send, to the first coherent agent, an indicator identifying a directory way that includes the entry. In response to a second coherent agent caching the cache block, the coherence directory may update the entry to include the second coherent agent. The first and second coherent agents may be configured to receive copies of the indicator, and to store their copy in locations associated with the cache block.

公开(公告)号：US20250103477A1

公开(公告)日：2025-03-27

申请号：US18819877

申请日：2024-08-29

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Jurgen M. Schulz ,  Tom Greenshtein ,  Elli Bagelman

IPC: G06F12/02 ,  G06F12/0815 ,  G06F12/12

Abstract: A memory controller circuit manages access to a memory cache circuit and storage circuits. The memory controller receives a memory access request, and attempts to reserve entries in a first set of storage circuits that are needed to process a cache hit prior to determining whether the memory access request hits in the memory cache circuit. This reservation attempt is performed without attempting to reserve other sets of storage circuits that are needed to process other possible outcomes of the memory access request, including a cache miss. If the memory controller circuit has successfully reserved entries in all of the first set of storage circuits, processing of the memory access request may be initiated. Conversely, if the memory controller is unable to reserve an entry in at least one of the first set of storage circuits, processing of the memory access request is inhibited.

公开(公告)号：US11586552B2

公开(公告)日：2023-02-21

申请号：US17320172

申请日：2021-05-13

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Tom Greenshtein

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0846 ,  G06F12/06 ,  G06F12/02 ,  G06F12/0862

Abstract: An apparatus includes a cache memory circuit configured to store a cache lines, and a cache controller circuit. The cache controller circuit is configured to receive a read request to an address associated with a portion of a cache line. In response to an indication that the portion of the cache line currently has at least a first sub-portion that is invalid and at least a second sub-portion that is modified relative to a version in a memory, the cache controller circuit is further configured to fetch values corresponding to the address from the memory, to generate an updated version of the portion of the cache line by using the fetched values to update the first sub-portion, but not the second sub-portion, of the portion of the cache line, and to generate a response to the read request that includes the updated version of the portion of the cache line.

公开(公告)号：US20220365881A1

公开(公告)日：2022-11-17

申请号：US17320172

申请日：2021-05-13

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Tom Greenshtein

IPC: G06F12/0891 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/02 ,  G06F12/06

Abstract: An apparatus includes a cache memory circuit configured to store a cache lines, and a cache controller circuit. The cache controller circuit is configured to receive a read request to an address associated with a portion of a cache line. In response to an indication that the portion of the cache line currently has at least a first sub-portion that is invalid and at least a second sub-portion that is modified relative to a version in a memory, the cache controller circuit is further configured to fetch values corresponding to the address from the memory, to generate an updated version of the portion of the cache line by using the fetched values to update the first sub-portion, but not the second sub-portion, of the portion of the cache line, and to generate a response to the read request that includes the updated version of the portion of the cache line.