公开(公告)号：US11893241B1

公开(公告)日：2024-02-06

申请号：US17823695

申请日：2022-08-31

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Sandeep Gupta ,  Chandan Shantharaj ,  Krishna C. Potnuru ,  Sahil Kapoor

IPC: G06F3/06 ,  G06F12/0877

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0877 ,  G06F2212/60

Abstract: A variable latency cache memory is disclosed. A cache subsystem includes a pipeline control circuit configured to initiate cache memory accesses for data. The cache subsystem further includes a cache memory circuit having a data array arranged into a plurality of groups, wherein different ones of the plurality of groups have different minimum access latencies due to different distances from the pipeline control circuit. A plurality of latency control circuits configured to ensure a latency is bounded to a maximum value for a given access to the data array, wherein a given latency control circuit is associated with a corresponding group of the plurality of groups. The latency for a given access may thus vary between a minimum access latency for a group closest to the pipeline control circuit to a maximum latency for an access to the group furthest from the pipeline control circuit.