公开(公告)号：US20210405174A1

公开(公告)日：2021-12-30

申请号：US16917852

申请日：2020-06-30

Applicant: Apple Inc.

Inventor： Michael KERNER ,  John Zhonghua WU ,  Michael DELISHANSKY ,  Zohar AGON ,  Shachar SHAYOVITZ ,  Michael NEY ,  Shay I. FREUNDLICH

IPC: G01S13/28 ,  G01S13/48 ,  G06F3/0354

Abstract: Accuracy for detecting and tracking one or more objects of interest can be improved using radar-based tracking systems. In some examples, multiple radars implemented in a device can be used to transmit signals to, and receive signals from, the one or more objects of interest. To disambiguate an object of interest from undesired objects such as the hand of a user, the object of interest can include a transponder that applies a delay element to a signal received from a radar, and thereafter transmits a delayed return signal back to the radar. The delay produced by the delay element can separate the return signal from undesired reflections and enable disambiguation of those signals. Clear identification of the desired return signal can lead to more accurate object distance determinations, more accurate triangulation, and improved position detection and tracking accuracy.

公开(公告)号：US20200083903A1

公开(公告)日：2020-03-12

申请号：US16126488

申请日：2018-09-10

Applicant: Apple Inc.

Inventor： Michael KERNER ,  Koby VAINAPEL ,  Shay GERSHONI

IPC: H03M13/11 ,  H04L1/18 ,  H04W72/08

Abstract: Some embodiments enable improved packet error rate (PER), signal to noise ratio (SNR), channel capacity, aggregated throughput, and communication range in wireless communication systems. For example, an electronic device includes a buffer that stores a first descrambled bit estimate sequence. The electronic device further includes an encoder that receives a descrambling sequence and generates an encoded descrambling sequence and a multiplier circuit that receives a bit estimate sequence and the encoded descrambling sequence and generates a second descrambled bit estimate sequence. The electronic device also includes an adder circuit that combines the first descrambled bit estimate sequence and the second descrambled bit estimate sequence and a decoder that decodes the combined descrambled bit estimate sequence.