公开(公告)号：US20230298302A1

公开(公告)日：2023-09-21

申请号：US17695038

申请日：2022-03-15

Applicant: Apple Inc.

Inventor： Assaf Metuki ,  Danny Gal ,  Liran Fishel

IPC: G06V10/46 ,  G06V10/74 ,  G06V10/75

CPC classification number: G06V10/46 ,  G06V10/751 ,  G06V10/761

Abstract: Embodiments of the present disclosure relate to sequentially loading keypoint descriptors of a previous image and comparing them with a plurality of keypoint descriptors of a current image. The keypoint descriptors of the previous image are stored and accessed from a system memory while the keypoint descriptors of the current image are stored and accessed from a local memory. Hence, the keypoint descriptors of the previous image are received only once at a descriptor match circuit while the keypoint descriptors of the current image are received multiple times for comparison against different keypoint descriptors of the previous image.

公开(公告)号：US11614937B1

公开(公告)日：2023-03-28

申请号：US17566193

申请日：2021-12-30

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Danny Gal ,  Nir Nissan ,  Etai Zaltsman

IPC: G06F9/30

Abstract: Embodiments of the present disclosure relate to an accelerator circuit with a dynamic immediate values table (IVT). The accelerator circuit includes an instruction memory, a data memory, and a vector circuit with the IVT storing multiple immediate values at multiple entries. The vector circuit reads a subset of instructions from the instruction memory, each instruction including at least one corresponding pointer to at least one corresponding entry in the IVT. The vector circuit further receives a subset of input data from the data memory corresponding to the subset of instructions. The vector circuit performs a respective operation in accordance with each instruction from the subset of instructions using a corresponding data vector of the received subset of input data identified in each instruction and at least one corresponding immediate value from the IVT pointed by the at least one corresponding pointer to generate corresponding output data.

公开(公告)号：US11507702B2

公开(公告)日：2022-11-22

申请号：US16674909

申请日：2019-11-05

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Zhimin Chen

IPC: G06F21/74 ,  G06F9/54 ,  G06F21/57 ,  G06N3/063

Abstract: Embodiments relate to switching a neural processor circuit between non-secure and secure modes. A security controller of the neural processor circuit indicates that a transition from the non-secure mode to the secure mode is to occur. The security controller waits for a neural task manager of the neural processor circuit to clear out any existing non-secure tasks in queues. After the existing non-secure mode tasks are cleared, the security controller switches the neural processor circuit to the secure mode. While in the secure mode, secure tasks are added to one or more queues and executed, and data for processing in the neural processor circuit is received from a secure source. The neural processor circuit may to transition back to the non-secure mode when all secure mode tasks are completed.

公开(公告)号：US20210133361A1

公开(公告)日：2021-05-06

申请号：US16674909

申请日：2019-11-05

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Zhimin Chen

IPC: G06F21/74 ,  G06F21/57 ,  G06N3/063 ,  G06F9/54

Abstract: Embodiments relate to switching a neural processor circuit between non-secure and secure modes. A security controller of the neural processor circuit indicates that a transition from the non-secure mode to the secure mode is to occur. The security controller waits for a neural task manager of the neural processor circuit to clear out any existing non-secure tasks in queues. After the existing non-secure mode tasks are cleared, the security controller switches the neural processor circuit to the secure mode. While in the secure mode, secure tasks are added to one or more queues and executed, and data for processing in the neural processor circuit is received from a secure source. The neural processor circuit may to transition back to the non-secure mode when all secure mode tasks are completed.

公开(公告)号：US12169959B2

公开(公告)日：2024-12-17

申请号：US17693007

申请日：2022-03-11

Applicant: Apple Inc.

Inventor： Assaf Metuki ,  Lukas Polok ,  Danny Gal ,  Liran Fishel

IPC: G06F17/00 ,  G06V10/74 ,  G06V10/75

Abstract: Embodiments of the present disclosure relate to selecting a subset of keypoint descriptors of two images for match operation based on their orientation angles indicated in headers of the keypoint descriptors. The keypoint descriptors in the two images are matched by first comparing their headers and then performing vector distance determination. During the header comparison operation, a header of a descriptor of a first image is compared only with headers of keypoint descriptors of a second image in a discrete orientation angle range corresponding to an orientation angle indicated by the header of the first image descriptor or keypoint descriptors of the second image in adjacent discrete orientation angle ranges. After the headers of the keypoint descriptors satisfying one or more matching criteria are determined, distance determination operations are performed between the keypoint descriptors while the remaining keypoint descriptors are discarded without determining their distances.

公开(公告)号：US11513848B2

公开(公告)日：2022-11-29

申请号：US17220703

申请日：2021-04-01

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Liran Fishel ,  Roman Gindin

IPC: G06F9/48 ,  G06F13/40

Abstract: In an embodiment, a system includes rate limiter circuits corresponding to various agents that issue transactions in a virtual channel. At least one agent may be identified as a critical agent, and different rate limits (e.g., lower limits) may be selected for other agents when the critical agent is on than when the critical agent is off (e.g., higher limits).

公开(公告)号：US11467988B1

公开(公告)日：2022-10-11

申请号：US17230490

申请日：2021-04-14

Applicant: Apple Inc.

Inventor： Per Hakan Hammarlund ,  Liran Fishel ,  Roman Gindin

IPC: G06F13/00 ,  G06F13/16 ,  G06F9/30 ,  G06F12/02

Abstract: Systems, apparatuses, and methods for implementing a memory fetch granule for real-time agents are described. A computing system includes a plurality of real-time agents coupled to memory via an interconnect fabric and a memory controller. The efficiency of the memory controller is determined by the number of bank groups in the memory devices coupled to the memory controller. A memory fetch granule is defined for the memory controller based on the amount of data that can be accessed in parallel on the memory device in back-to-back access cycles. Each real-time agent accumulates memory requests for sequential physical addresses until the amount of data referenced by the requests reaches the size of the memory fetch granule. Once the memory fetch granule is reached, the real-time agent sends the requests to the memory controller via the fabric. This helps to ensure that the requests will arrive at the memory controller near enough to each other to get grouped together.

公开(公告)号：US20220107836A1

公开(公告)日：2022-04-07

申请号：US17220703

申请日：2021-04-01

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Liran Fishel ,  Roman Gindin

IPC: G06F9/48 ,  G06F13/40

Abstract: In an embodiment, a system includes rate limiter circuits corresponding to various agents that issue transactions in a virtual channel. At least one agent may be identified as a critical agent, and different rate limits (e.g., lower limits) may be selected for other agents when the critical agent is on than when the critical agent is off (e.g., higher limits).

公开(公告)号：US11120327B2

公开(公告)日：2021-09-14

申请号：US15971657

申请日：2018-05-04

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Sung Hee Park ,  Christopher L. Mills

IPC: G06N3/04

Abstract: Embodiments relate to a neural processor circuit that includes a kernel access circuit and multiple neural engine circuits. The kernel access circuit reads compressed kernel data from memory external to the neural processor circuit. Each neural engine circuit receives compressed kernel data from the kernel access circuit. Each neural engine circuit includes a kernel extract circuit and a kernel multiply-add (MAD) circuit. The kernel extract circuit extracts uncompressed kernel data from the compressed kernel data. The kernel MAD circuit receives the uncompressed kernel data from the kernel extract circuit and performs neural network operations on a portion of input data using the uncompressed kernel data.

公开(公告)号：US20190340488A1

公开(公告)日：2019-11-07

申请号：US15971657

申请日：2018-05-04

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Sung Hee Park ,  Christopher L. Mills

IPC: G06N3/04

Abstract: Embodiments relate to a neural processor circuit that includes a kernel access circuit and multiple neural engine circuits. The kernel access circuit reads compressed kernel data from memory external to the neural processor circuit. Each neural engine circuit receives compressed kernel data from the kernel access circuit. Each neural engine circuit includes a kernel extract circuit and a kernel multiply-add (MAD) circuit. The kernel extract circuit extracts uncompressed kernel data from the compressed kernel data. The kernel MAD circuit receives the uncompressed kernel data from the kernel extract circuit and performs neural network operations on a portion of input data using the uncompressed kernel data.