公开(公告)号：US20250103122A1

公开(公告)日：2025-03-27

申请号：US18807525

申请日：2024-08-16

Applicant: Apple Inc.

Inventor： Angel E. Socarras ,  Ben D. Jarrett ,  Jason P. Jane ,  Thomas B. Pringle ,  Andrea Gianarro ,  Jackson Dsouza

IPC: G06F1/3206 ,  G06F11/34 ,  G06F11/36

Abstract: Techniques are disclosed relating to power management in a processing circuit that includes a set of functional blocks and performance counter registers configured to store utilization values indicative of utilization of associated ones of the set of functional blocks. A register interface circuit is configured to periodically sample the processing circuit to obtain aggregated utilization values generated from utilization values stored in the performance counter registers and write the aggregated utilization values to the set of trace buffer. A power management processor is configured to utilize a set of information stored in the set of trace buffers to determine whether to change a performance state of the processing circuit, the set of information including time-domain and frequency-domain representations of utilization of the processing circuit. In other embodiments, a functional block that is a hardware limiter of the processing circuit may be determined.