公开(公告)号：US10152434B2

公开(公告)日：2018-12-11

申请号：US15385566

申请日：2016-12-20

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Rostyslav Kyrychynskyi ,  Anthony Asaro ,  Kostantinos Danny Christidis ,  Mark Fowler ,  Michael J. Mantor ,  Robert Scott Hartog

IPC: G06F13/14 ,  G06F13/16 ,  G06F13/36 ,  G06F13/40

Abstract: A system and method for efficient arbitration of memory access requests are described. One or more functional units generate memory access requests for a partitioned memory. An arbitration unit stores the generated requests and selects a given one of the stored requests. The arbitration unit identifies a given partition of the memory which stores a memory location targeted by the selected request. The arbitration unit determines whether one or more other stored requests access memory locations in the given partition. The arbitration unit sends each of the selected memory access request and the identified one or more other memory access requests to the memory to be serviced out of order.

公开(公告)号：US10579388B2

公开(公告)日：2020-03-03

申请号：US16040224

申请日：2018-07-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Robert Scott Hartog ,  Mark Leather ,  Michael Mantor ,  Rex McCrary ,  Sebastien Nussbaum ,  Philip J. Rogers ,  Ralph Clay Taylor ,  Thomas Woller

IPC: G06F9/38 ,  G06F9/48 ,  G06T1/20

Abstract: A method for use in a processor for arbitrating between multiple processes to select wavefronts for execution on a shader core is provided. The processor includes a compute pipeline configured to issue wavefronts to the shader core for execution, a hardware queue descriptor associated with the compute pipeline, and the shader core. The shader core is configured to execute work for the compute pipeline corresponding to a first memory queue descriptor executed using data for the first memory queue descriptor that is loaded into a first hardware queue descriptor. The processor is configured to detect a context switch condition, and, responsive to the context switch condition, perform a context switch operation including loading data for a second memory queue descriptor into the first hardware queue descriptor. The shader core is configured to execute work corresponding to the second memory queue descriptor that is loaded into the first hardware queue descriptor.

公开(公告)号：US10242420B2

公开(公告)日：2019-03-26

申请号：US15362230

申请日：2016-11-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Robert Scott Hartog ,  Ralph Clayton Taylor ,  Michael Mantor ,  Kevin John McGrath ,  Sebastien Nussbaum ,  Nuwan Jayasena ,  Rex McCrary ,  Mark Leather ,  Philip J. Rogers ,  Thomas Woller

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/52 ,  G06T1/60

Abstract: Methods and apparatus are described. A method includes an accelerated processing device running a process. When a maximum time interval during which the process is permitted to run expires before the process completes, the accelerated processing device receives an operating-system-initiated instruction to stop running the process. The accelerated processing device stops the process from running in response to the received operating-system-initiated instruction.

公开(公告)号：US20170076421A1

公开(公告)日：2017-03-16

申请号：US15362230

申请日：2016-11-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Robert Scott Hartog ,  Ralph Clayton Taylor ,  Michael Mantor ,  Kevin John McGrath ,  Sebastien Nussbaum ,  Nuwan Jayasena ,  Rex McCrary ,  Mark Leather ,  Philip J. Rogers ,  Thomas Woller

IPC: G06T1/20 ,  G06F9/52 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/4881 ,  G06F9/526 ,  G06T1/60

Abstract: Methods and apparatus are described. A method includes an accelerated processing device running a process. When a maximum time interval during which the process is permitted to run expires before the process completes, the accelerated processing device receives an operating-system-initiated instruction to stop running the process. The accelerated processing device stops the process from running in response to the received operating-system-initiated instruction.

Abstract translation: 描述了方法和装置。 一种方法包括运行处理的加速处理装置。 当进程完成之前允许进程允许的最大时间间隔到期时，加速处理装置接收操作系统启动的指令以停止运行该进程。 加速处理装置响应于接收到的操作系统发起的指令而停止进程运行。

公开(公告)号：US20180173649A1

公开(公告)日：2018-06-21

申请号：US15385566

申请日：2016-12-20

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Rostyslav Kyrychynskyi ,  Anthony Asaro ,  Kostantinos Danny Christidis ,  Mark Fowler ,  Michael J. Mantor ,  Robert Scott Hartog

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/161 ,  G06F13/1673 ,  G06F13/4068

Abstract: A system and method for efficient arbitration of memory access requests are described. One or more functional units generate memory access requests for a partitioned memory. An arbitration unit stores the generated requests and selects a given one of the stored requests. The arbitration unit identifies a given partition of the memory which stores a memory location targeted by the selected request. The arbitration unit determines whether one or more other stored requests access memory locations in the given partition. The arbitration unit sends each of the selected memory access request and the identified one or more other memory access requests to the memory to be serviced out of order.

公开(公告)号：US20180321946A1

公开(公告)日：2018-11-08

申请号：US16040224

申请日：2018-07-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Robert Scott Hartog ,  Mark Leather ,  Michael Mantor ,  Rex McCrary ,  Sebastien Nussbaum ,  Philip J. Rogers ,  Ralph Clay Taylor ,  Thomas Woller

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/48

CPC classification number: G06F9/3851 ,  G06F9/3879 ,  G06F9/4881 ,  G06T1/20

Abstract: A method for use in a processor for arbitrating between multiple processes to select wavefronts for execution on a shader core is provided. The processor includes a compute pipeline configured to issue wavefronts to the shader core for execution, a hardware queue descriptor associated with the compute pipeline, and the shader core. The shader core is configured to execute work for the compute pipeline corresponding to a first memory queue descriptor executed using data for the first memory queue descriptor that is loaded into a first hardware queue descriptor. The processor is configured to detect a context switch condition, and, responsive to the context switch condition, perform a context switch operation including loading data for a second memory queue descriptor into the first hardware queue descriptor. The shader core is configured to execute work corresponding to the second memory queue descriptor that is loaded into the first hardware queue descriptor.