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公开(公告)号：US20240004664A1
公开(公告)日：2024-01-04
申请号：US17855727
申请日：2022-06-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Sree Harsha Kosuru , Eric Dixon , Erik Swanson , Michael Estlick , Patrick Michael Lowry
CPC classification number: G06F9/384 , G06F9/30123
Abstract: The disclosed system may include a processor configured to detect that a data unit size for an instruction is smaller than a register. The processor may allocate a first portion of the register to the instruction in a manner that leaves a second portion of the register available for allocating to an additional instruction. The processor may also track the register as a split register. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US11573801B1
公开(公告)日：2023-02-07
申请号：US17489301
申请日：2021-09-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Eric Dixon , Erik Swanson , Theodore Carlson , Ruchir Dalal , Michael Estlick
Abstract: A processor includes a register file and control logic that detects multiple different sets of sequential zero bits of a register in the register file, wherein each of the multiple different sets has a bit length that corresponds to a partial instruction width and operates at a first partial instruction width or a second partial instruction width with the register file depending on number of sets of zero bits detected in the register. In certain examples, the control logic causes operating at first instruction width that avoids merging of a first bit length of data in the register and operating at the second instruction width that avoids merging of a second bit length of data in the register. In some examples, a register rename map table incudes multiple zero bits that identify the detected multiple different sets of bits of sequential zeros.
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公开(公告)号：US11960897B2
公开(公告)日：2024-04-16
申请号：US17389838
申请日：2021-07-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael Estlick , Erik Swanson , Eric Dixon , Todd Baumgartner
CPC classification number: G06F9/3869 , G06F9/30123
Abstract: In some implementations, a processor includes a plurality of parallel instruction pipes, a register file includes at least one shared read port configured to be shared across multiple pipes of the plurality of parallel instruction pipes. Control logic controls multiple parallel instruction pipes to read from the at least one shared read port. In certain examples, the at least one shared register file read port is coupled as a single read port for one of the parallel instruction pipes and as a shared register file read port for a plurality of other parallel instruction pipes.
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Patent Agency Ranking
公开(公告)号：US12229563B2
公开(公告)日：2025-02-18
申请号：US17855727
申请日：2022-06-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Sree Harsha Kosuru , Eric Dixon , Erik Swanson , Michael Estlick , Patrick Michael Lowry
Abstract: The disclosed system may include a processor configured to detect that a data unit size for an instruction is smaller than a register. The processor may allocate a first portion of the register to the instruction in a manner that leaves a second portion of the register available for allocating to an additional instruction. The processor may also track the register as a split register. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US12223324B2
公开(公告)日：2025-02-11
申请号：US17957604
申请日：2022-09-30
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Michael Estlick , Eric Dixon , Theodore Carlson , Erik D. Swanson
Abstract: A data processing system includes a vector data processing unit that includes a shared scheduler queue configured to store in a same queue, at least one entry that includes at least a mask type instruction and another entry that includes at least a vector type instruction. Shared pipeline control logic controls a vector data path or a mask data path, based a type of instruction picked from the same queue. In some examples, at least one mask type instruction and the at least one vector type instruction each include a source operand having a corresponding shared source register bit field that indexes into both a mask register file and a vector register file. The shared pipeline control logic uses a mask register file or a vector register file depending on whether bits of the shared source register bit field identify a mask source register or a vector source register.
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公开(公告)号：US12204935B2
公开(公告)日：2025-01-21
申请号：US17390149
申请日：2021-07-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael Estlick , Erik Swanson , Eric Dixon
Abstract: Methods, systems, and apparatuses provide support for allowing thread forward progress in a processing system and that improves quality of service. One system includes a processor; a bus coupled to the processor; a memory coupled to the processor via the bus; and a floating point unit coupled to the processor via the bus, wherein floating point unit comprises hardware control logic operative to: store for each thread, by a scheduler of the floating point unit, a counter; increase, by the scheduler, a value of the counter for each thread corresponding to a thread when at least one source ready operation exist for the thread; compare, by the scheduler, the value of the counter to a predetermined threshold; and make other threads ineligible to be picked by the scheduler when the counter is greater than or equal to the predetermined threshold.
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公开(公告)号：US20230034933A1
公开(公告)日：2023-02-02
申请号：US17390149
申请日：2021-07-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael Estlick , Erik Swanson , Eric Dixon
Abstract: Methods, systems, and apparatuses provide support for allowing thread forward progress in a processing system and that improves quality of service. One system includes a processor; a bus coupled to the processor; a memory coupled to the processor via the bus; and a floating point unit coupled to the processor via the bus, wherein floating point unit comprises hardware control logic operative to: store for each thread, by a scheduler of the floating point unit, a counter; increase, by the scheduler, a value of the counter for each thread corresponding to a thread when at least one source ready operation exist for the thread; compare, by the scheduler, the value of the counter to a predetermined threshold; and make other threads ineligible to be picked by the scheduler when the counter is greater than or equal to the predetermined threshold.
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公开(公告)号：US20230034072A1
公开(公告)日：2023-02-02
申请号：US17389838
申请日：2021-07-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael Estlick , Erik Swanson , Eric Dixon , Todd Baumgartner
Abstract: In some implementations, a processor includes a plurality of parallel instruction pipes, a register file includes at least one shared read port configured to be shared across multiple pipes of the plurality of parallel instruction pipes. Control logic controls multiple parallel instruction pipes to read from the at least one shared read port. In certain examples, the at least one shared register file read port is coupled as a single read port for one of the parallel instruction pipes and as a shared register file read port for a plurality of other parallel instruction pipes.
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