ACCELERATING PREDICATED INSTRUCTION EXECUTION IN VECTOR PROCESSORS

    公开(公告)号:US20240004656A1

    公开(公告)日:2024-01-04

    申请号:US17853790

    申请日:2022-06-29

    CPC classification number: G06F9/30145 G06F9/3851 G06F9/3887

    Abstract: Methods and systems are disclosed for processing a vector by a vector processor. Techniques disclosed include receiving predicated instructions by a scheduler, each of which is associated with an opcode, a vector of elements, and a predicate. The techniques further include executing the predicated instructions. Executing a predicated instruction includes compressing, based on an index derived from a predicate of the instruction, elements in a vector of the instruction, where the elements in the vector are contiguously mapped, then, after the mapped elements are processed, decompressing the processed mapped elements, where the processed mapped elements are reverse mapped based on the index.

    Accelerating predicated instruction execution in vector processors

    公开(公告)号:US12164923B2

    公开(公告)日:2024-12-10

    申请号:US17853790

    申请日:2022-06-29

    Abstract: Methods and systems are disclosed for processing a vector by a vector processor. Techniques disclosed include receiving predicated instructions by a scheduler, each of which is associated with an opcode, a vector of elements, and a predicate. The techniques further include executing the predicated instructions. Executing a predicated instruction includes compressing, based on an index derived from a predicate of the instruction, elements in a vector of the instruction, where the elements in the vector are contiguously mapped, then, after the mapped elements are processed, decompressing the processed mapped elements, where the processed mapped elements are reverse mapped based on the index.

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