公开(公告)号：US07716521B1

公开(公告)日：2010-05-11

申请号：US11123674

申请日：2005-05-06

申请人： Hunter S. Donahue ,  Ricky C. Hetherington ,  Jimmy K. Lau

发明人： Hunter S. Donahue ,  Ricky C. Hetherington ,  Jimmy K. Lau

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3879 ,  G06F9/3885 ,  G06F11/0715 ,  G06F11/0721 ,  G06F11/0724

摘要： A multiple-core, multithreaded processor including a flexible error steering mechanism. An integrated circuit may include processor cores. Each processor core is associated with a respective number of threads and is configured to issue a first instruction from one of the threads during one execution cycle and a second instruction from another one of the threads during a successive execution cycle. An error processing unit may be coupled to the processor cores and configured to detect an error condition corresponding to a data element external to the processor cores. In response to detecting the error condition, the error processing unit may convey an indication of the error to a selected processor core dependent upon an identifier of the selected core. The error indication may also include an identifier of a selected thread executable on the selected processor core. The identifiers of the selected core and the selected thread may be programmable.

摘要翻译： 一个多核多线程处理器，包括一个灵活的错误转向机制。 集成电路可以包括处理器核。 每个处理器核心与相应数量的线程相关联，并且被配置为在一个执行周期期间从一个线程发出第一条指令，并且在连续的执行周期期间从另一个线程发出第二条指令。 错误处理单元可以耦合到处理器核并且被配置为检测与处理器核心外部的数据元素相对应的错误状况。 响应于检测到错误状况，错误处理单元可以根据所选择的核心的标识符将错误的指示传送到所选择的处理器核心。 错误指示还可以包括在所选择的处理器核心上可执行的所选线程的标识符。 所选择的核心和所选线程的标识符可以是可编程的。

公开(公告)号：US07657807B1

公开(公告)日：2010-02-02

申请号：US11167248

申请日：2005-06-27

申请人： Daniel R. Watkins ,  Hunter S. Donahue ,  Thomas Alan Ziaja

发明人： Daniel R. Watkins ,  Hunter S. Donahue ,  Thomas Alan Ziaja

IPC分类号： G01R31/28

CPC分类号： G01R31/318594

摘要： An integrated circuit including embedded test functionality. An integrated circuit may include a plurality of processor cores each configured to execute instructions, and a test access port configured to interface circuits included within the integrated circuit with a test environment external to the integrated circuit for testing of the circuits. The test access port may include virtualization logic configured to allow a first set of instructions executing on the given processor core to control activity of the test access port for testing of the circuits. In one embodiment, the circuits may be accessible for testing via a plurality of scan chains, wherein the scan chains and the test access port are compliant with a version of Joint Test Access Group (JTAG) standard IEEE 1149, and wherein the test access port includes a Test Data In (TDI) pin, a Test Data Out (TDO) pin, and a Test Clock (TCK) pin.

摘要翻译： 包含嵌入式测试功能的集成电路。 集成电路可以包括被配置为执行指令的多个处理器核心以及被配置为将集成电路中包括的电路与用于电路测试的集成电路外部的测试环境接合的测试访问端口。 测试访问端口可以包括虚拟化逻辑，其被配置为允许在给定处理器核上执行的第一组指令来控制用于测试电路的测试访问端口的活动。 在一个实施例中，电路可以通过多个扫描链进行测试，其中扫描链和测试访问端口符合联合测试访问组（JTAG）标准IEEE 1149的版本，并且其中测试访问端口 包括测试数据输入（TDI）引脚，测试数据输出（TDO）引脚和测试时钟（TCK）引脚。