- 专利标题: Electrical interconnect formed through buildup process
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申请号: US13717048申请日: 2012-12-17
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公开(公告)号: US09955589B2公开(公告)日: 2018-04-24
- 发明人: Mihir K Roy , Matthew J Manusharow
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwegman Lundberg & Woessner, P.A.
- 主分类号: H05K3/46
- IPC分类号: H05K3/46 ; H05K3/40 ; H01L23/498 ; H01L21/48 ; H05K3/10 ; H01L23/538 ; H05K1/18
摘要:
This disclosure relates generally to an electronic chip package that can include a die and a buildup layer substantially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the buildup layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic chip package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic chip package different from the first major surface.
公开/授权文献
- US10028394B2 Electrical interconnect formed through buildup process 公开/授权日:2018-07-17
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