- 专利标题: MUX for SerDes transmitter having low data jitter
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申请号: US14315268申请日: 2014-06-25
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公开(公告)号: US09954630B1公开(公告)日: 2018-04-24
- 发明人: Karthik C. Venna
- 申请人: Xilinx, Inc.
- 申请人地址: US CA San Jose
- 专利权人: XILINX, INC.
- 当前专利权人: XILINX, INC.
- 当前专利权人地址: US CA San Jose
- 代理商 Gerald Chan; Carleton Clauss; Keith Taboada
- 主分类号: H04J3/06
- IPC分类号: H04J3/06
摘要:
A multiplexer (MUX) configured to receive a plurality of input data streams and output an output data stream via an output data line based at least in part upon a control signal, includes: a first circuit portion corresponding to a first data stream of the plurality of input data streams, comprising: a first internal node; a first control switch operable to connect the output data line to the first internal node of the first circuit portion based at least in part upon the control signal, wherein the first internal node has a value corresponding to the first data stream when the output data line is connected to the first internal node; and a first reset switch operable to connect the first internal node to a common mode voltage rail based at least in part upon the control signal to remove or reduce residual charge at the first internal node.
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