According to one embodiment, a semiconductor memory device includes a cell transistor coupled to a word line, a sense amplifier configured to output data based on a state of the cell transistor in response to a first signal asserted; and a controller configured to apply a voltage of a magnitude continuously rising to the word line, and periodically assert the first signal after a lapse of any selected one of a first time and a second time from the start of rise of the magnitude of the voltage. The first time is different from the second time.