- 专利标题: Planar memory cell architectures in resistive memory devices
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申请号: US15138477申请日: 2016-04-26
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公开(公告)号: US09953705B2公开(公告)日: 2018-04-24
- 发明人: Daniel Bedau
- 申请人: HGST Netherlands B.V.
- 申请人地址: US CA San Jose
- 专利权人: WESTERN DIGITAL TECHNOLOGIES, INC.
- 当前专利权人: WESTERN DIGITAL TECHNOLOGIES, INC.
- 当前专利权人地址: US CA San Jose
- 主分类号: G11C11/00
- IPC分类号: G11C11/00 ; G11C13/00 ; H01L45/00 ; H01L23/528 ; H01L27/24
摘要:
To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive random access memory (ReRAM) array is provided. The ReRAM array includes a plurality of memory cells each comprising resistive memory material formed into a layer of a substrate, with resistance properties of the resistive memory material corresponding to data bits stored by the memory cells. The ReRAM array also includes a plurality of interconnect features each comprising conductive material between adjacent memory cells formed into the layer of the substrate, and gate portions coupled onto the memory cells and configured to individually alter the resistance properties of the resistive memory material of associated memory cells responsive to at least voltages applied to the gate portions.
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