This application discloses a computing system to implement a design verification tool and simulate a circuit design with a regression. The computing system can define coverage for system level functionality of a circuit design as a set of system level coverage points. Each of the system level coverage points can correspond to a different portion of system level functionality of the circuit design. The computing system can correlate the system level coverage points in the set according to characteristics of the different portions of the system level functionality corresponding to the system level coverage points. The computing system can utilize the correlated set of system level coverage points to identify system level functionality left uncovered by events performed by the circuit design during simulation with one or more regressions.