HEVC video encoder and decoder for multi-core
摘要:
The disclosure provides a video encoder. The video encoder receives a frame and divides the frame into a plurality of tiles. The video encoder includes a plurality of video processing engines communicatively coupled with each other. Each video processing engine receives a tile of the plurality of tiles. A height of each tile is equal to a height of the frame and each tile comprises a plurality of rows. The plurality of video processing engines includes a first and a second video processing engine. The second video processing engine being initiated after the first video processing engines processes M rows of the plurality of rows of the tile, where M is an integer.
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