Invention Grant
- Patent Title: Integrated circuit with backside structures to reduce substrate warp
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Application No.: US14881365Application Date: 2015-10-13
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Publication No.: US09646938B2Publication Date: 2017-05-09
- Inventor: Chih-Ming Chen , Szu-Yu Wang , Chung-Yi Yu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/02 ; H01L27/108 ; H01L49/02 ; H01L21/302 ; H01L21/822

Abstract:
Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.
Public/Granted literature
- US20160035682A1 INTEGRATED CIRCUIT WITH BACKSIDE STRUCTURES TO REDUCE SUBSTRATE WARP Public/Granted day:2016-02-04
Information query
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