A memory device includes a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction crossing the first direction, and a plurality of memory cells. Each memory cell includes a memory element and two select transistors disposed along the first direction and the memory element being configured to store information based on changes in resistance. A first and a second column are formed by repeatedly arranging a first group and a second group of the memory cells, respectively, along the first direction, and the second column is disposed adjacent to the first column and the first group is displaced in the first direction such that, in the second direction, a first select transistor in respective memory cells in the first column is aligned with a second select transistor in respective memory cells in the second column.