Invention Grant
US09559002B2 Methods of fabricating semiconductor devices with blocking layer patterns
有权
制造具有阻挡层图案的半导体器件的方法
- Patent Title: Methods of fabricating semiconductor devices with blocking layer patterns
- Patent Title (中): 制造具有阻挡层图案的半导体器件的方法
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Application No.: US14804831Application Date: 2015-07-21
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Publication No.: US09559002B2Publication Date: 2017-01-31
- Inventor: Seung-Taek Lee , Eun-Ji Kim , Sin-Woo Kang , Yeong-Lyeol Park , Sung-Dong Cho
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel, P.A.
- Priority: KR10-2014-0091907 20140721
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/308 ; H01L21/3105 ; H01L21/762 ; H01L23/48 ; H01L25/065 ; H01L23/522 ; H01L21/8234 ; H01L23/532
Abstract:
A semiconductor device includes a circuit device on a substrate and a first insulating interlayer on the substrate and covering the circuit device. An electrode structure extends through the first insulating interlayer and at least partially through the substrate. An etch-stop layer pattern is disposed on a sidewall of the electrode structure on a side of the first insulating layer opposite the substrate. A blocking layer pattern is disposed on the etch-stop layer pattern. The device further includes an interconnection structure including a via portion passing through the blocking layer pattern to contact the through electrode structure and a wiring portion on the via portion and having a different width than the via portion. The semiconductor device may further include a contact plug electrically connected to the circuit device through the first insulating interlayer. The contact plug and the through electrode structure may include different metals.
Public/Granted literature
- US20160020145A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH BLOCKING LAYER PATTERNS Public/Granted day:2016-01-21
Information query
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