Invention Grant
US09514093B2 Method and apparatus for stacking core and uncore dies having landing slots
有权
用于堆叠具有着陆槽的芯和裸芯片的方法和装置
- Patent Title: Method and apparatus for stacking core and uncore dies having landing slots
- Patent Title (中): 用于堆叠具有着陆槽的芯和裸芯片的方法和装置
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Application No.: US14498353Application Date: 2014-09-26
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Publication No.: US09514093B2Publication Date: 2016-12-06
- Inventor: Stefan Rusu
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson de Vos Webster & Elliot LLP
- Main IPC: G06F15/76
- IPC: G06F15/76 ; H01L25/065

Abstract:
An apparatus and method are described for stacking a plurality of cores. For example, one embodiment of an apparatus comprises: a package; an uncore die mounted on the package, the uncore die comprising a plurality of exposed landing slots, each landing slot including an inter-die interface usable to connect vertically to a cores die, the uncore die including a plurality of uncore components usable by cores within the cores die including a memory controller component, a level 3 (L3) cache, a system memory or system memory interface, and a core interconnect fabric or bus; and a first cores die comprising a first plurality of cores, the cores spaced on the first cores die to correspond to all or a first subset of the landing slots on the uncore die, each of the cores having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the first cores die is vertically coupled on top of the uncore die, wherein the communicative coupling between the inter-die interface of a core and the inter-die interface of its corresponding landing slot communicatively couples the core to the uncore components of the uncore die.
Public/Granted literature
- US20160092396A1 METHOD AND APPARATUS FOR STACKING A PLURALITY OF CORES Public/Granted day:2016-03-31
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