Transmission circuit for transmitting serial data with superposed clock signal includes encoder to scramble parallel data of information and apply predetermined coding scheme to generate D symbols having clock signal embedded therein, and to output alternately continuous predetermined number of the D symbols and one of K symbols as synchronization control codes for the scrambling; and parallel-to-serial converter configured to convert the D symbols and the K symbols output from the encoder into serial data, wherein, for each period of the scrambling, the encoder outputs K symbols, each of which is allocated to one of the first code indicating beginning of the period of the scrambling, the second code allocated at equal interval among remaining ones of the K symbols other than that for the first code, and a third code allocated among remaining ones of the K symbols other than those for the first code and the second code.