发明授权
US09396135B2 Method and apparatus for improving computer cache performance and for protecting memory systems against some side channel attacks
有权
用于提高计算机缓存性能并保护存储器系统免受某些侧面信道攻击的方法和装置
- 专利标题： Method and apparatus for improving computer cache performance and for protecting memory systems against some side channel attacks
- 专利标题（中）： 用于提高计算机缓存性能并保护存储器系统免受某些侧面信道攻击的方法和装置
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申请号： US13458145申请日： 2012-04-27
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公开(公告)号： US09396135B2公开(公告)日： 2016-07-19
- 发明人: Krishna M. Kavi
- 申请人： Krishna M. Kavi
- 申请人地址： US TX Denton
- 专利权人： University of North Texas
- 当前专利权人： University of North Texas
- 当前专利权人地址： US TX Denton
- 代理机构： Chalker Flores, LLP
- 代理商 Daniel J. Chalker; Edwin S. Flores
- 主分类号： G06F12/00
- IPC分类号： G06F12/00 ; G06F12/06 ; G06F12/08 ; G06F13/00 ; G06F13/28 ; G06F12/14
摘要：
A physical cache memory that is divided into one or more virtual segments using multiple circuits to decode addresses is provided. An address mapping and an address decoder is selected for each virtual segment. The address mapping comprises two or more address bits as set indexes for the virtual segment and the selected address bits are different for each virtual segment. A cache address decoder is provided for each virtual segment to enhance execution performance of programs or to protect against the side channel attack. Each physical cache address decoder comprises an address mask register to extract the selected address bits to locate objects in the virtual segment. The foregoing can be implemented as a method or apparatus for protecting against a side channel attack.
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