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US09395739B2 Common well bias design for a driving circuit and method of using same 有权
驱动电路的通用阱偏置设计及其使用方法

Common well bias design for a driving circuit and method of using same
摘要：
A driving circuit includes a common well. The driving circuit further includes a first output buffer having a bulk connected to the common well, the first output buffer having a first terminal configured to receive a first signal, and having a second terminal connected to the common well. The driving circuit further includes a second output buffer having a bulk connected to the common well, the second output buffer having a first terminal configured to receive the first signal, wherein a second terminal of the second output buffer is disconnected from the common well.
摘要（中）：

驱动电路包括公共井。 所述驱动电路还包括具有连接到所述公共阱的体的第一输出缓冲器，所述第一输出缓冲器具有被配置为接收第一信号的第一端子，以及连接到所述公用阱的第二端子。 所述驱动电路还包括具有大体连接到所述公共井的第二输出缓冲器，所述第二输出缓冲器具有被配置为接收所述第一信号的第一端子，其中所述第二输出缓冲器的第二端子与所述公共井断开连接。

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