发明授权
US09385708B2 Methodology to avoid gate stress for low voltage devices in FDSOI technology
有权
在FDSOI技术中避免低压器件栅极应力的方法
- 专利标题： Methodology to avoid gate stress for low voltage devices in FDSOI technology
- 专利标题（中）： 在FDSOI技术中避免低压器件栅极应力的方法
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申请号： US14216701申请日： 2014-03-17
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公开(公告)号： US09385708B2公开(公告)日： 2016-07-05
- 发明人: Ankit Agrawal
- 申请人： STMicroelectronics International N.V.
- 申请人地址： NL Amsterdam
- 专利权人： STMicroelectronics International N.V.
- 当前专利权人： STMicroelectronics International N.V.
- 当前专利权人地址： NL Amsterdam
- 代理机构： Seed IP Law Group PLLC
- 主分类号： H01L27/12
- IPC分类号： H01L27/12 ; H01L29/786 ; H03K3/00 ; H03K17/687 ; H03K17/10 ; H01L29/10 ; H01L29/423 ; H01L27/092
摘要：
An inverter is implemented in an FDSOI integrated circuit die. The inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter.
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