发明授权
US09385083B1 Wafer-level die to package and die to die interconnects suspended over integrated heat sinks
有权
晶圆级芯片封装和裸芯片连接在一起散布在散热片上
- 专利标题: Wafer-level die to package and die to die interconnects suspended over integrated heat sinks
- 专利标题(中): 晶圆级芯片封装和裸芯片连接在一起散布在散热片上
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申请号: US14720619申请日: 2015-05-22
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公开(公告)号: US09385083B1公开(公告)日: 2016-07-05
- 发明人: Florian G. Herrault , Melanie S. Yajima , Alexandros Margomenos , Miroslav Micovic
- 申请人: HRL Laboratories, LLC
- 申请人地址: US CA Malibu
- 专利权人: HRL Laboratories, LLC
- 当前专利权人: HRL Laboratories, LLC
- 当前专利权人地址: US CA Malibu
- 代理机构: Ladas & Parry
- 主分类号: H01L21/00
- IPC分类号: H01L21/00 ; H01L23/10 ; H01L23/528 ; H01L23/36 ; H01L21/768 ; H01L23/532 ; H05K7/20
摘要:
An interconnect for electrically coupling pads formed on adjacent chips or on packaging material adjacent the chips, with an electrically conductive heat sink being disposed between the pads, the interconnect comprising a metallic membrane layer disposed between two adjacent pads and disposed or bridging over the electrically conductive heat sink so as to avoid making electrical contact with the electrically conductive heat sink. An electroplated metallic layer is disposed on the metallic membrane layer. Fabrication of interconnect permits multiple interconnects to be formed in parallel using fabrication techniques compatible with wafer level fabrication of the interconnects. The interconnects preferably follow a smooth curve to electrically connect adjacent pads and following that smooth curve they bridge over the intervening electrically conductive heat sink material in a predictable fashion.
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