发明授权
- 专利标题: Electronic circuit, electronic apparatus, and authentication system
- 专利标题(中): 电子电路,电子仪器和认证系统
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申请号: US14521616申请日: 2014-10-23
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公开(公告)号: US09384682B2公开(公告)日: 2016-07-05
- 发明人: Dai Yamamoto , Masahiko Takenaka
- 申请人: FUJITSU LIMITED
- 申请人地址: JP Kawasaki
- 专利权人: FUJITSU LIMITED
- 当前专利权人: FUJITSU LIMITED
- 当前专利权人地址: JP Kawasaki
- 代理机构: Staas & Halsey LLP
- 优先权: JP2013-246421 20131128
- 主分类号: H04L9/08
- IPC分类号: H04L9/08 ; G09C1/00 ; H03K3/037
摘要:
An electronic circuit includes: a plurality of RS latch circuits each configured to enter a metastable state in accordance with a clock signal input to the RS latch circuit; a determination circuit configured to determine whether an output of each of the RS latch circuits is a random number or a fixed number; and a selector configured to select whether to maintain the clock signal input to the RS latch circuit, to change the clock signal input to the RS latch circuit to another clock signal having a different frequency, or to input a clock signal for fixing a signal output from the RS latch circuit, as the clock signal input to the RS latch circuit, in accordance with a result determined by the determination circuit.
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