发明授权
- 专利标题: Techniques for enhancing fracture resistance of interconnects
- 专利标题(中): 提高互连抗断裂性的技术
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申请号: US13753245申请日: 2013-01-29
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公开(公告)号: US09343411B2公开(公告)日: 2016-05-17
- 发明人: Christopher J. Jezewski , Mauro J. Kobrinsky , Daniel Pantuso , Siddharth B. Bhingarde , Michael P. O'Day
- 申请人: INTEL CORPORATION
- 申请人地址: US CA Santa Clara
- 专利权人: INTEL CORPORATION
- 当前专利权人: INTEL CORPORATION
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Finch & Maloney PLLC
- 主分类号: H01L23/522
- IPC分类号: H01L23/522 ; H01L23/528 ; H01L23/535 ; H01L23/538 ; H01L23/62 ; H01L23/00 ; H01L23/29
摘要:
Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.
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