发明授权
US09310432B2 Method and system for measuring the impedance of the power distribution network in programmable logic device applications 有权
用于测量可编程逻辑器件应用中配电网络阻抗的方法和系统

  • 专利标题: Method and system for measuring the impedance of the power distribution network in programmable logic device applications
  • 专利标题(中): 用于测量可编程逻辑器件应用中配电网络阻抗的方法和系统
  • 申请号: US13465024
    申请日: 2012-05-06
  • 公开(公告)号: US09310432B2
    公开(公告)日: 2016-04-12
  • 发明人: Cosmin Iorga
  • 申请人: Cosmin Iorga
  • 主分类号: G01R27/00
  • IPC分类号: G01R27/00 G01R31/317 G01R31/3185
Method and system for measuring the impedance of the power distribution network in programmable logic device applications
摘要:
On-die measurement of power distribution impedance frequency profile of a programmable logic device (PLD), such as field programmable gate array (FPGA) or complex programmable logic device (CPLD), is performed by configuring and using only logic blocks resources commonly available in any existing programmable logic device, without the need of built-in dedicated circuits. All measurements are done inside the programmable logic device without the need of external instruments. The measurement method can be used during characterization to select decoupling capacitors or for troubleshooting existing systems, after which the programmable logic device may be reconfigured to perform any other user-defined function.
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