发明授权
US09208836B1 Chip-to-chip signaling with improved bandwidth utilization 有权
片上信令与带宽利用率提高

  • 专利标题: Chip-to-chip signaling with improved bandwidth utilization
  • 专利标题(中): 片上信令与带宽利用率提高
  • 申请号: US13345987
    申请日: 2012-01-09
  • 公开(公告)号: US09208836B1
    公开(公告)日: 2015-12-08
  • 发明人: Frederick A. Ware
  • 申请人: Frederick A. Ware
  • 申请人地址: US CA Sunnyvale
  • 专利权人: Rambus Inc.
  • 当前专利权人: Rambus Inc.
  • 当前专利权人地址: US CA Sunnyvale
  • 代理商 Charles Shemwell
  • 主分类号: G11C7/10
  • IPC分类号: G11C7/10
Chip-to-chip signaling with improved bandwidth utilization
摘要:
Integrated circuit devices transmit data via a shared signaling link in back to back burst intervals without contention and without insertion of performance-degrading bubbles by disabling output drivers during an interval that occurs at an edge or “margin” of a given burst interval and thus at a timing boundary between the back to back burst intervals. In “bit-level margining” embodiments, the driver-disabling operation or “margining” is performed during a portion of each bit interval (i.e., a unit of time allocated to transmission of a bit or other symbol. In “burst-level margining” embodiments, output drivers are disabled over an entire bit interval that occurs at the margin of a given burst interval.
信息查询
0/0