发明授权
- 专利标题： Integrated circuit layout
- 专利标题（中）： 集成电路布局
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申请号： US13834495申请日： 2013-03-15
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公开(公告)号： US09030025B2公开(公告)日： 2015-05-12
- 发明人: Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
- 申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
- 申请人地址： TW Hsinchu
- 专利权人： IPEnval Consultant Inc.
- 当前专利权人： IPEnval Consultant Inc.
- 当前专利权人地址： TW Hsinchu
- 代理机构： Kamrath IP Lawfirm, P.A.
- 代理商 Alan D. Kamrath
- 主分类号： H01L23/48
- IPC分类号： H01L23/48
摘要：
An integrated circuit layout comprises a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV), a through silicon via (TSV) configured to couple operational signals (signal TSV), a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) around the VDD TSV and the signal TSV and one or more backside redistribution lines (RDLs) connecting the VSS TSVs together to form a web-like heat dissipating structure at least surrounding the VDD TSV and the signal TSV.
公开/授权文献
- US20140264918A1 Integrated Circuit Layout 公开/授权日：2014-09-18
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