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US09030015B2 Three dimensional stacked structure for chips 有权
芯片三维堆叠结构

Three dimensional stacked structure for chips
摘要:
A 3-D chip stacked structure is disclosed. Each chip layer is provided with plural single-layered conductive members where among the same chip layer the two adjacent conductive members are structurally formed in mirror symmetric way with each other along a chip longitudinal direction and the arrangements of the single-layered conductive members of the two adjacent chip layers are shifted by a test pad distance. The single-layered conductive members of the two adjacent chip layers are communicated through a vertical TSV (through silicon via). Therefore, a selection signal or an enabling signal might be transferred through this specific metal layer and related TSV to reach targeting chip layer and targeting circuit.
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