Invention Grant
US09015557B2 Simultaneous data transfer and error control to reduce latency and improve throughput to a host
有权
同时进行数据传输和错误控制,以减少主机的延迟并提高吞吐量
- Patent Title: Simultaneous data transfer and error control to reduce latency and improve throughput to a host
- Patent Title (中): 同时进行数据传输和错误控制,以减少主机的延迟并提高吞吐量
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Application No.: US14150667Application Date: 2014-01-08
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Publication No.: US09015557B2Publication Date: 2015-04-21
- Inventor: Christopher J. Sarcone , David G. Conroy , Jim Keller
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Womble Carlyle Sandridge & Rice , LLP
- Main IPC: G11C29/00
- IPC: G11C29/00 ; H04L1/08 ; G06F11/10 ; H04L1/00

Abstract:
The disclosed embodiments provide a system that transfers data from a storage device to a host. The system includes a communication mechanism that receives a request to read a set of blocks from the host. Next, upon reading each block from the set of blocks from the storage device, the communication mechanism transfers the block over an interface with the host. The system also includes an error-detection apparatus that performs error detection on the block upon reading the block, and an error-correction apparatus that performs error correction on the block if an error is detected in the block. The communication mechanism may then retransfer the block to the host after the error is removed from the block.
Public/Granted literature
- US20140195872A1 SIMULTANEOUS DATA TRANSFER AND ERROR CONTROL TO REDUCE LATENCY AND IMPROVE THROUGHPUT TO A HOST Public/Granted day:2014-07-10
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