Invention Grant
US09015500B2 Method and apparatus for using dynamic voltage and frequency scaling with circuit-delay based integrated circuit identification
有权
使用基于电路延迟的集成电路识别的动态电压和频率缩放的方法和装置
- Patent Title: Method and apparatus for using dynamic voltage and frequency scaling with circuit-delay based integrated circuit identification
- Patent Title (中): 使用基于电路延迟的集成电路识别的动态电压和频率缩放的方法和装置
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Application No.: US13743239Application Date: 2013-01-16
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Publication No.: US09015500B2Publication Date: 2015-04-21
- Inventor: Xu Guo , Liangguo Shen
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP
- Main IPC: G06F21/73
- IPC: G06F21/73 ; G06F1/26 ; H04L9/32 ; H04L9/08

Abstract:
One feature pertains to a method that includes implementing a Physical Unclonable Function (PUF) circuit, and obtaining a first set of output bits from the PUF circuit by operating the PUF circuit at a first supply voltage level and/or first frequency. Then, at least one of the first supply voltage level is changed to a second supply voltage level and/or the first frequency is changed to a second frequency, where the second supply voltage level and the second frequency are different than the first supply voltage level and the first frequency, respectively. A second set of output bits is then obtained by operating the PUF circuit at the second supply voltage level and/or the second frequency, where the second set of output bits is in part different than the first set. Secure data is generated using the first set of output bits and the second sets of output bits.
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