发明授权
- 专利标题: Methods, systems, and articles of manufacture for implementing a physical electronic design with area-bounded tracks
- 专利标题(中): 用于实施带区域轨迹的物理电子设计的方法,系统和制品
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申请号: US13931503申请日: 2013-06-28
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公开(公告)号: US09003349B1公开(公告)日: 2015-04-07
- 发明人: Jeffrey Salowe
- 申请人: Cadence Design Systems, Inc.
- 申请人地址: US CA San Jose
- 专利权人: Cadence Design Systems, Inc.
- 当前专利权人: Cadence Design Systems, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Vista IP Law Group, LLP
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
Disclosed are methods, systems, and articles of manufacture for implementing a physical electronic design with area-bounded tracks. One aspect identifies an area in an electronic design and a track pattern associated with the area, identifies active tracks in the track pattern, and creates spacetiles with the active tracks. This aspect uses area-based search probes based on spacetiles to find viable implementation solutions to implement the area in the electronic design. Another aspect identifies a tracked area associated with a track pattern and a trackless area and use spacetile(s) and a via spacetile layer to transition between the tracked area and the trackless area for implementation of the electronic design in the tracked or the trackless area of the electronic design.
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