Invention Grant
- Patent Title: Methods, systems, and apparatus for reliability synthesis
- Patent Title (中): 用于可靠性合成的方法，系统和装置
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Application No.: US12047540Application Date: 2008-03-13
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Publication No.: US08856700B1Publication Date: 2014-10-07
- Inventor: Yosinori Watanabe , Walter J. Ghijsen , Michael J. Meyer , Michael T. Y. McNamara , David Van Campenhout
- Applicant: Yosinori Watanabe , Walter J. Ghijsen , Michael J. Meyer , Michael T. Y. McNamara , David Van Campenhout
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Alford Law Group, Inc.
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
In one embodiment of the invention, a method of synthesizing a circuit design is disclosed including receiving an input model of an initial circuit design into an electronic design automation system; receiving a user specification detailing a reliability feature to add to the initial circuit design; adding the reliability feature to the input model based upon the user specification to generate a modified input model; and producing an output model of a circuit design with the reliability feature in response to the modified input model.
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