发明授权
- 专利标题： PLL (phase-locked loop)
- 专利标题（中）： PLL（锁相环）
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申请号： US13461101申请日： 2012-05-01
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公开(公告)号： US08742810B2公开(公告)日： 2014-06-03
- 发明人: Hiroki Noguchi , Keiko Abe , Shinichi Yasuda , Shinobu Fujita
- 申请人： Hiroki Noguchi , Keiko Abe , Shinichi Yasuda , Shinobu Fujita
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- 优先权： JP2011-166073 20110728
- 主分类号： H03L7/06
- IPC分类号： H03L7/06
摘要：
One embodiment provides a phase-locked loop (PLL), in which a sequencer controls a loop filter such that, when a signal indicating turning-off of a power supply of the PLL is input thereto, or when a signal indicating turning-on of the power supply of the PLL is input thereto, a resistance value of a first resistance change device in the loop filter is a first resistance value, and that, after the PLL is stabilized, the resistance value of the first resistance change device is a second resistance value which is higher than the first resistance value.
公开/授权文献
- US20130027093A1 PLL 公开/授权日：2013-01-31
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