A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the resistance-based memory element at a first operating point of the sensing circuit.