发明授权
US08614143B2 Simultaneous via and trench patterning using different etch rates
有权
使用不同蚀刻速率的同时通孔和沟槽图案化
- 专利标题: Simultaneous via and trench patterning using different etch rates
- 专利标题(中): 使用不同蚀刻速率的同时通孔和沟槽图案化
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申请号: US12327336申请日: 2008-12-03
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公开(公告)号: US08614143B2公开(公告)日: 2013-12-24
- 发明人: Makarand R. Kulkarni , Deepak A. Ramappa
- 申请人: Makarand R. Kulkarni , Deepak A. Ramappa
- 申请人地址: US TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: US TX Dallas
- 代理商 Warren L. Franz; Wade J. Brady, III; Frederick J. Telecky, Jr.
- 主分类号: H01L21/4763
- IPC分类号: H01L21/4763
摘要:
One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal.
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