A circuit comprises an inverter, a first transistor, a second transistor, and at least one switching circuit. The inverter has a first node and a second node. The first transistor has a first terminal, a second terminal, and a third terminal. The second transistor has a fourth terminal, a fifth terminal, and a sixth terminal. The at least one switching circuit is configured to switch a connection of at least one of the first transistor and the second transistor to the inverter. The second terminal and the fifth terminal are coupled to the first node. The third terminal and the sixth terminal are coupled to the second node. The first transistor and the second transistor are configured to cause a plurality of time delays at the second node.