A delay library generation apparatus, associated control method, and associated program are provided. The delay library generation apparatus comprises a storage device which stores architecture information of a logic element array, layout data of an overall programmable logic device, a netlist of the overall programmable logic device, and a wiring route extraction unit which refers to the storage device and extracts wiring route information regarding a wiring route section based on the architecture information. Moreover, the delay library generation apparatus comprises an analyzing unit which analyzes the layout data of the logic device and extracts parameters of a parasitic element and a crosstalk between adjacent interconnections. The delay generation apparatus further comprises a delay calculation unit which calculates delay data based on the extracted parameters and a delay library generation unit which generates a delay library of the logic device based on the wiring route information and the delay data.