发明授权
US08499139B2 Avoiding stall in processor pipeline upon read after write resource conflict when intervening write present
有权
在写入资源冲突时，在读写时避免在处理器管道中停止写入
- 专利标题： Avoiding stall in processor pipeline upon read after write resource conflict when intervening write present
- 专利标题（中）： 在写入资源冲突时，在读写时避免在处理器管道中停止写入
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申请号： US12855201申请日： 2010-08-12
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公开(公告)号： US08499139B2公开(公告)日： 2013-07-30
- 发明人: Leonid Dubrovin , Alexander Rabinovitch , Hagit Margolin , Noam Abda
- 申请人： Leonid Dubrovin , Alexander Rabinovitch , Hagit Margolin , Noam Abda
- 申请人地址： US CA San Jose
- 专利权人： LSI Corporation
- 当前专利权人： LSI Corporation
- 当前专利权人地址： US CA San Jose
- 代理机构： Christopher P. Maiorana, PC
- 主分类号： G06F9/38
- IPC分类号： G06F9/38
摘要：
An apparatus having a processor and a circuit is disclosed. The processor generally has a pipeline. The circuit may be configured to (i) detect a first write instruction in the pipeline that writes to a resource, (ii) stall a read instruction in the pipeline where (a) a first read-after-write conflict exists between the first write instruction and the read instruction and (b) no other write instruction to the resource is scheduled between the first write instruction and the read instruction and (iii) not stall the read instruction due to the first read-after-write conflict where a second write instruction to the resource is scheduled between the first write instruction and the read instruction.
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