Approaches for generating a hardware specification from a high-level language (HLL) program. In one approach, a method determines separate accesses in the HLL program to multiple consecutively addressed data items. The HLL program is compiled into an intermediate language program to include one or more instructions that perform functions on the multiple consecutively addressed data items and one or more memory access instructions that reference the consecutively addressed data items. The method generates a hardware specification from the intermediate language program. The hardware specification includes a cache memory that caches the consecutively addressed data items and that accesses the consecutively addressed data items in response to a single access request. The specification further includes one or more hardware blocks that implement the functions of the instructions in the intermediate language program. At least one of hardware blocks has access to the multiple consecutively addressed data items in parallel.