发明授权
- 专利标题: Semiconductor integrated circuit with multi-cut via and automated layout method for the same
- 专利标题(中): 半导体集成电路采用多通孔和自动布局方式相同
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申请号: US13586070申请日: 2012-08-15
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公开(公告)号: US08418109B2公开(公告)日: 2013-04-09
- 发明人: Keiichi Nishimuda
- 申请人: Keiichi Nishimuda
- 申请人地址: JP Kawasaki-shi, Kanagawa
- 专利权人: Renesas Electronics Corporation
- 当前专利权人: Renesas Electronics Corporation
- 当前专利权人地址: JP Kawasaki-shi, Kanagawa
- 代理机构: McGinn IP Law Group, PLLC
- 优先权: JP2007-74005 20070322
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; H01L23/522
摘要:
A semiconductor integrated circuit includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first overlap area, a second overlap area, a multi-cut via, the multi-cut via including a first via and a second via formed in the first direction, and a single-cut via formed to connect the third wiring to the fourth wiring in the second overlap area. A width of the second portion of the second wiring corresponding to a first direction is longer than a width of the first portion of the second wiring corresponding to the first direction. A distance between the center of the first via and the center of the second via is longer than the width of the first portion of second wiring.
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