发明授权
- 专利标题: Delay locked loop
- 专利标题(中): 延迟锁定环路
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申请号: US13190841申请日: 2011-07-26
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公开(公告)号: US08368446B2公开(公告)日: 2013-02-05
- 发明人: Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
- 申请人: Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
- 申请人地址: KR Gyeonggi-do
- 专利权人: Hynix Semiconductor Inc.
- 当前专利权人: Hynix Semiconductor Inc.
- 当前专利权人地址: KR Gyeonggi-do
- 代理机构: IP & T Group LLP
- 优先权: KR10-2011-0037203 20110421
- 主分类号: H03L7/06
- IPC分类号: H03L7/06
摘要:
A delay locked loop includes a delay unit delaying an input clock to generate an output clock, a replica delay unit delaying the output clock to generate a feedback clock, a phase comparing unit outputting a phase signal having a first or second value according to whether the phase of the feedback clock leads the phase of the input clock, a filtering unit generates a filtering signal in response to the phase signal and updates the filtering signal when a difference of count numbers of the phase signal having the first value and the second value is substantially equal to a filtering depth, a locking unit generates a locking signal in response to the filtering signal, and a control unit adjusts a delay value in response to the filtering signal and maintains the delay value when the locking signal is activated.
公开/授权文献
- US20120268180A1 DELAY LOCKED LOOP 公开/授权日:2012-10-25
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