Invention Grant
- Patent Title: Semiconductor substrate planarization apparatus and planarization method
- Patent Title (中): 半导体衬底平面化装置和平面化方法
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Application No.: US12748109Application Date: 2010-03-26
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Publication No.: US08366514B2Publication Date: 2013-02-05
- Inventor: Satoru Ide , Moriyuki Kashiwa , Kazuo Kobayashi , Noriyuki Motimaru , Eiichi Yamamoto , Tomio Kubo , Hiroaki Kida
- Applicant: Satoru Ide , Moriyuki Kashiwa , Kazuo Kobayashi , Noriyuki Motimaru , Eiichi Yamamoto , Tomio Kubo , Hiroaki Kida
- Applicant Address: JP Annaka
- Assignee: Okamoto Machine Tool Works, Ltd.
- Current Assignee: Okamoto Machine Tool Works, Ltd.
- Current Assignee Address: JP Annaka
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-001727 20100107
- Main IPC: B24B1/00
- IPC: B24B1/00 ; B24B5/02

Abstract:
A planarization apparatus and method that thins and planarizes a substrate by grinding and polishing the rear surface of the substrate with high throughput, and that fabricates a semiconductor substrate with reduced adhered contaminants. A planarization apparatus that houses various mechanism elements in semiconductor substrate loading/unloading stage chamber, a rear-surface polishing stage chamber, and a rear-surface grinding stage chamber. The throughput time of the rear-surface polishing stage that simultaneously polishes two substrates is typically about double the throughput time of the rear-surface grinding stage that grinds one substrate.
Public/Granted literature
- US20110165823A1 SEMICONDUCTOR SUBSTRATE PLANARIZATION APPARATUS AND PLANARIZATION METHOD Public/Granted day:2011-07-07
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