发明授权
US08361838B2 Semiconductor package and method for manufacturing the same via holes in semiconductor chip for plurality stack chips
有权
用于制造用于多个堆叠芯片的半导体芯片中的相同通孔的半导体封装和方法
- 专利标题: Semiconductor package and method for manufacturing the same via holes in semiconductor chip for plurality stack chips
- 专利标题(中): 用于制造用于多个堆叠芯片的半导体芯片中的相同通孔的半导体封装和方法
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申请号: US13241812申请日: 2011-09-23
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公开(公告)号: US08361838B2公开(公告)日: 2013-01-29
- 发明人: Seung Taek Yang , Min Suk Suh , Seung Hyun Lee , Jong Hoon Kim
- 申请人: Seung Taek Yang , Min Suk Suh , Seung Hyun Lee , Jong Hoon Kim
- 申请人地址: KR Gyeonggi-do
- 专利权人: Hynix Semiconductor Inc.
- 当前专利权人: Hynix Semiconductor Inc.
- 当前专利权人地址: KR Gyeonggi-do
- 代理机构: Ladas & Parry LLP
- 优先权: KR10-2008-0023041 20080312
- 主分类号: H01L21/00
- IPC分类号: H01L21/00 ; H01L23/48
摘要:
A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip.
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