Invention Grant
US08258012B2 Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die
有权
在半导体管芯之间形成不连续的ESD保护层的半导体器件和方法
- Patent Title: Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die
- Patent Title (中): 在半导体管芯之间形成不连续的ESD保护层的半导体器件和方法
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Application No.: US12780295Application Date: 2010-05-14
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Publication No.: US08258012B2Publication Date: 2012-09-04
- Inventor: Reza A. Pagaila , Jose A. Caparas , Pandi C. Marimuthu
- Applicant: Reza A. Pagaila , Jose A. Caparas , Pandi C. Marimuthu
- Applicant Address: SG Singapore
- Assignee: Stats ChipPAC, Ltd.
- Current Assignee: Stats ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins & Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/552
- IPC: H01L23/552

Abstract:
A semiconductor wafer has a plurality of semiconductor die separated by a saw street. The wafer is mounted to dicing tape. The wafer is singulated through the saw street to expose side surfaces of the semiconductor die. An ESD protection layer is formed over the semiconductor die and around the exposed side surfaces of the semiconductor die. The ESD protection layer can be a metal layer, encapsulant film, conductive polymer, conductive ink, or insulating layer covered by a metal layer. The ESD protection layer is singulated between the semiconductor die. The semiconductor die covered by the ESD protection layer are mounted to a temporary carrier. An encapsulant is deposited over the ESD protection layer covering the semiconductor die. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The ESD protection layer is electrically connected to the interconnect structure to provide an ESD path.
Public/Granted literature
- US20110278703A1 Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor Die Public/Granted day:2011-11-17
Information query
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