Invention Grant
- Patent Title: Method for using digital PLL in a voltage regulator
- Patent Title (中): 在电压调节器中使用数字PLL的方法
-
Application No.: US12564466Application Date: 2009-09-22
-
Publication No.: US08159276B2Publication Date: 2012-04-17
- Inventor: Gustavo James Mehas , Sandeep Agarwal , Jayant Vivrekar , Xiaole Chen
- Applicant: Gustavo James Mehas , Sandeep Agarwal , Jayant Vivrekar , Xiaole Chen
- Applicant Address: US CA Milpitas
- Assignee: Intersil Americas Inc.
- Current Assignee: Intersil Americas Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Howison & Arnott, L.L.P.
- Main IPC: H03L7/06
- IPC: H03L7/06
Abstract:
A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.
Public/Granted literature
- US20100007391A1 METHOD FOR USING DIGITAL PLL IN A VOLTAGE REGULATOR Public/Granted day:2010-01-14
Information query
