知搜-全球专利检索

  1. 登录
  2. 注册
发明授权
US08156317B2 Integrated circuit with secure boot from a debug access port and method therefor 有权
具有来自调试接入端口的安全引导的集成电路及其方法

Integrated circuit with secure boot from a debug access port and method therefor
摘要：
An integrated circuit (100) may receive a boot loader code (114) via a debug access port (105), wherein a boot logic is operative to block, upon a reset (123) of the programmable processor (103) from the debug access port (105), commands and to the programmable processor from the debug access port, while still allowing the reset (123) command and while allowing write access to memory (112) to receive the boot loader code image (114) written to memory (112). The boot logic also blocks commands to the memory subsystem (109) from the debug access port and turns off write access to memory (112) after allowing the boot loader code image (114) to be written. The boot logic validates the boot loader code image (114) by performing a security check and jumps to the boot loader code image (114) if it is valid, thereby allowing it to run on the programmable processor (103). The boot logic may be logic circuits, software or a combination thereof.
摘要（中）：

集成电路（100）可以经由调试访问端口（105）接收引导加载程序代码（114），其中启动逻辑可操作以在可编程处理器（103）的复位（123）从调试访问 端口（105），命令和来自调试访问端口的可编程处理器，同时仍然允许复位（123）命令，同时允许对存储器（112）的写访问以接收写入存储器的引导加载程序代码映像（114） 112）。 引导逻辑还从调试访问端口阻止对存储器子系统（109）的命令，并且在允许写入引导加载程序代码映像（114）之后，关闭对存储器（112）的写访问。 启动逻辑通过执行安全检查来验证引导加载程序代码映像（114），并且如果其有效则跳转到引导加载程序代码映像（114），从而允许其在可编程处理器（103）上运行。 引导逻辑可以是逻辑电路，软件或其组合。

公开/授权文献
信息查询
Espacenet
0/0