发明授权
US08006068B1 Processor access to data cache with fixed or low variable latency via instructions to an auxiliary processing unit
有权
处理器通过指令到辅助处理单元访问具有固定或低可变延迟的数据高速缓存
- 专利标题： Processor access to data cache with fixed or low variable latency via instructions to an auxiliary processing unit
- 专利标题（中）： 处理器通过指令到辅助处理单元访问具有固定或低可变延迟的数据高速缓存
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申请号： US11787926申请日： 2007-04-18
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公开(公告)号： US08006068B1公开(公告)日： 2011-08-23
- 发明人: Glenn C. Steiner
- 申请人： Glenn C. Steiner
- 申请人地址： US CA San Jose
- 专利权人： Xilinx, Inc.
- 当前专利权人： Xilinx, Inc.
- 当前专利权人地址： US CA San Jose
- 代理商 W. Eric Webostad; LeRoy D. Maunu
- 主分类号： G06F15/76
- IPC分类号： G06F15/76
摘要：
Access to data storage is described. A general-purpose processor and an auxiliary processing unit (APU) interface coupled to the general-purpose processor are provided. Data storage coupled to the general-purpose processor via the APU interface is provided for a fixed or low variable read latency access and a fixed write latency access to the data storage. A first instruction is passed to the general-purpose processor and to the APU interface. The first instruction is identified as part of a set of instructions accessible by the APU interface. The first instruction is used to write data into the data storage. A second instruction is passed to the general-purpose processor and to the APU interface. The second instruction is identified as part of the set of instructions accessible by the APU interface. The second instruction is used to read the data from the data storage, and the data is then output.
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